The editorial argues that taping out a leading-node ASIC in nine months is genuinely unusual and that OpenAI's vague attribution to its own models accelerating RTL generation, verification, and floorplan optimization is the kind of marketing claim that needs specifics. Plausible candidates like SystemVerilog generation, coverage-closure, and timing-driven placement hints are credible only when stacked together, not individually.
Bluntly notes that without details on which specific parts of the design flow were model-accelerated, the nine-month claim reads as marketing rather than substance. Wants OpenAI to disclose where AI actually shaved time off the cadence.
Immediately flagged that OpenAI's official post is quiet about the foundry, pointing to outside reporting confirming TSMC (not Intel Foundry) is the manufacturing partner. The implication is that OpenAI is deliberately downplaying the TSMC dependency, possibly for geopolitical or PR reasons around US foundry ambitions.
Argues the 'another hyperscaler builds its own chip' framing underplays the story — what matters is that OpenAI chose inference first, unlike Google's training-heavy TPU trajectory. The chip is purpose-built for OpenAI's production serving shapes: long-context decode, MoE routing, and speculative decoding, signaling that serving cost, not training cost, is now the binding constraint.
Submitted the TechCrunch piece framing Jalapeño as a Broadcom-built custom chip designed for OpenAI's specific inference workload needs. Treats this as a confirmation of the now-familiar pattern where the customer owns workload-specific microarchitecture and Broadcom provides SerDes, packaging, and HBM integration.
OpenAI unveiled Jalapeño, its first custom silicon, co-designed with Broadcom and fabricated at TSMC. The chip is purpose-built for inference — not training — and targets the specific shapes of OpenAI's production serving stack (long-context decode, MoE routing, speculative decoding). The company says the design went from architecture to tape-out in roughly nine months, a timeline OpenAI attributes in part to using its own models to accelerate parts of RTL generation, verification, and floorplan optimization.
The official post is conspicuously quiet about the foundry. Hacker News commenter `shellcromancer` flagged the omission immediately, pointing to reporting that confirms TSMC, not Intel Foundry, is the manufacturing partner. Broadcom's role appears to be the standard hyperscaler-ASIC pattern: OpenAI owns the microarchitecture and the workload-specific IP; Broadcom provides SerDes, packaging, HBM integration, and the physical-design muscle to actually get a chip out the door.
The nine-month claim is the part that deserves scrutiny — taping out a leading-node ASIC that fast, even with a partner like Broadcom, is genuinely unusual, and "our models helped" is the kind of line that needs receipts before it's worth taking at face value. Commenter `sharkjacobs` made the same point bluntly: without details on *which* parts of the flow were model-accelerated, the claim reads as marketing. Plausible candidates: SystemVerilog generation from a spec, coverage-closure on verification, and timing-driven placement hints. None of those would shave nine months off a normal cadence on their own, but stacked together they're credible.
The immediate read is "another hyperscaler builds its own chip," and that's true but underplays it. The more interesting framing is what kind of chip OpenAI chose to build first. Google started with training (TPU v1 was inference, but v2 onward leaned training-heavy). Amazon split the line into Trainium and Inferentia. Meta's MTIA has been inference-first from the start. OpenAI is following the Meta playbook, not the Google one — and that's a tell about where the unit economics hurt.
Training is a capex problem you solve once per model generation; inference is an opex problem you pay every token, forever, and at ChatGPT's scale a 30% cost-per-token reduction is worth more than a marginal training speedup. Nvidia knows this, which is why Blackwell's inference story (FP4, NVLink Switch, disaggregated serving) got most of the GTC oxygen. But Nvidia's margins on H100/B200 are the entire point of owning your own inference silicon — even a chip that's *worse* per FLOP than Blackwell wins if it's 3-4x cheaper per delivered token on your specific workload mix.
The community immediately reached for the more radical version of this idea. Commenter `londons_explore` floated weights-in-ROM: "one multiplier per weight... the whole thing turns into a bunch of simple adders... one token per clock cycle." That's not quite buildable for a 1T-parameter MoE — you'd need the reticle of a small planet — but it's the asymptote everyone in inference-ASIC land is pointed at. Startups like Taalas (mentioned by `nickpinkston`) are pursuing exactly this: burn the model into silicon, keep a small SRAM region for fine-tuning, eat the flexibility loss for a 10-100x latency/cost win. Jalapeño is almost certainly *not* that — it's a programmable accelerator, because OpenAI ships a new model every few months and can't afford to respin a mask set each time — but the existence of Jalapeño makes the Taalas thesis more credible, not less.
Then there's the Google comparison. `maz1b` in the thread: "Google and their TPUs are looking infinitely more prescient... they are on their 7th generation." That's the right instinct. TPU v7 (Ironwood) shipped earlier this year with ~4,614 TFLOPs FP8 per chip and pod-scale ICI fabric; OpenAI's v1 is, generously, where Google was around TPU v3. The gap isn't insurmountable — Broadcom has done the heavy lifting for Google for years and knows the playbook — but anyone expecting Jalapeño to instantly close the efficiency delta with Ironwood is going to be disappointed. The point isn't to beat Google's silicon. The point is to stop paying Nvidia 70% gross margins on every inference request.
For most teams reading this: nothing, directly, for at least 18 months. Jalapeño is internal-only. There's no "Jalapeño instance type" coming to Azure tomorrow, and even if OpenAI eventually exposes it (the way Google exposed TPU via Cloud TPU), it'll show up as a cheaper inference SKU for OpenAI's own API — not as a chip you provision.
What *does* change, and quickly: the price floor for frontier-model inference. If OpenAI's per-token cost drops 30-50% on internal hardware, expect the API price cuts to follow within two quarters — Anthropic, Google, and the open-weights serving crowd (Together, Fireworks, Groq) will have to respond. If you're building anything where token cost is the dominant line item — agents, RAG-heavy products, anything with long context — start modeling 2027 unit economics with a 40-60% lower inference cost than today. That changes which products are viable. It also changes the calculus on self-hosting Llama/Qwen/DeepSeek: the gap between "run your own" and "hit the API" is about to widen again in favor of the API.
For anyone in the hardware-adjacent layer of the stack — vLLM, SGLang, TensorRT-LLM, custom CUDA kernels — the proliferation of non-Nvidia inference silicon is the story. PyTorch's compiler story (Inductor, AOTInductor) and the OpenAI-driven Triton are increasingly the portability layer. Kernels written against CUDA intrinsics are getting more expensive to maintain, not less.
The Jalapeño announcement is best read as the end of the Nvidia-only era for frontier inference, not as a moonshot. Google has been there for a decade, AWS for half of one, Meta for years. OpenAI was the conspicuous holdout, and the holdout status was untenable the moment ChatGPT inference became the largest line item in the company's compute bill. Expect a v2 in 12-18 months that closes part of the gap with Ironwood, a v3 that exposes capacity to enterprise customers via Azure, and a Broadcom revenue line that quietly becomes one of the most important numbers in the semiconductor industry.
Announcement: <a href="https://openai.com/index/openai-broadcom-jalapeno-inference-chip/" rel="nofollow">https://openai.com/index/openai-broadcom-jalapeno-
→ read on Hacker NewsProbably obvious but still omitted in the OpenAI post: chips are being made by TSMC [1]. Wasn't sure if Intel got it.1. https://www.investing.com/news/stock-market-news/openai-unve...
This is very cool to see - seems like soooo much efficiency waiting to be unlocked at the chip level.What's everyone think of Taalas?They're actually burning the LLM model into the silicon, with some onboard memory for fine-tuning. They claim huge cost / latency wins.Super fast demo l
I wanna see an inference chip where the weights are part of the rom of the chip.There would be 1 multiplier per weight (and since they're constant, the whole thing turns into a bunch of simple adders), and the total pipelined system throughput would be one token per clock cycle.That means you c
Pretty huge move. Google and their TPUs are looking infinitely more prescient as I think they are on their 7th generation, along with the offshoots it inspired like the LPU and even others, perhaps like Cerebras and their Wafer Scale Engine.However, based off first impressions, it seems like this is
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> Developed from design to production in nine months, accelerated by OpenAI’s models> the use of OpenAI models to accelerate parts of the design and optimization process.I wish there was more about this. As is I kind of have to assume that this is just meaningless marketing, like saying develo